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HIP7030A0
PRELIMINARY
April 1994
J1850 8-Bit 68HC05 Microcontroller Emulator Version
Description
The HIP7030A0 Emulator is functionally equivalent to the HIP7030A2 microcontroller with the addition of external data bus, address bus, and control signals which provide off chip address capability. It is designed to permit prototype and pre-production development of systems for mask programmed applications. The HIP7030A0 is also intended for construction of development systems for the HIP7030A2.
Features
* HIP7030A2 Microcontroller Emulation - All HIP7030A2 Hardware and Software Features - Timing and Performance Equivalent to HIP7030A2 * On-Chip Memory - 176 Bytes of RAM - No ROM * Full 8K Byte Address Space Available Externally * Non-Multiplexed External Address and Data Lines - I/O Memory Interface Matches Industry Standard EPROM/EEPROMS for True Emulation with Two Chips * FS Line Identifies Fetch Cycles for Breakpoint Logic * -40oC to +125oC Operating Range * Single 3.0V to 6.0V Supply * Available in 68 Lead PLCC Packages
Ordering Information
PART NUMBER HIP7030A0M TEMPERATURE RANGE -40oC to +125oC PACKAGE 68 Lead Plastic LCC
Pinout
HIP7030A0 (PLCC) TOP VIEW
CE NC NC FS RD A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 9 8 7 6 5 4 3 2 1 6867666564636261 NC NC WE DS ALC PD4 PD3 PD2 PD1 PD0 NC NC VSS OSCOUT OSCIN SCK MOSI 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27282930313233 34 35 36 37 38 39 40 41 42 43 NC NC NC NC NC MISO SS TCAP TCMP VPWIN VPWOUT RESET IRQ VDD NC PA7 PA6 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 A12 NC DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 OSCB PA0 PA1 PA2 PA3 PA4 PA5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3645
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HIP7030A0 Block Diagram
TCMP 35 TCAP PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PD0 PD1 PD2, V2 PD3, V3 PD4, VR TCAP DS WE CE FS RD ALC PORT A I/O LINES 34 49 48 47 46 45 44 43 42 19 PORT D I/O LINES 18 17 16 15 TIMER SYSTEM INTERNAL PROCESSOR CLOCK OSCIN OSCOUT 24 OSCILLATOR AND / 2 23 50 OSCB 38 39
RESET IRQ
PORT A REG
DATA DIR REG
ACCUMULATOR 8 8 5 INDEX REGISTER CONDITION CODE REGISTER STACK POINTER A X CC S ALU CPU CONTROL
SYMBOL INT 37 VPW SYMBOL ENCODER / DECODER AND ARBITRATION 36 VPWOUT VPWIN
CPU
PORT D REG +
6 PORT D SFR REG PORT D DIR REG 5 8
32 SPI SYSTEM 26 25 33
-
PROGRAM COUNTER HIGH PCH PROGRAM COUNTER LOW PCL
SCK MOSI MISO SS
+
13 12 9 6 5 14 58 57 56 BUS CONTROL BUS DRIVE 49 48 47 46 55 54 53 52 51 176 x 8 STATIC RAM
INTERNAL PROCESSOR CLOCK WATCHDOG AND SLOW CLOCK DETECT
ADDRESS DRIVE 45 44 43 42 49 48 47 46 A10 45 A12 A11
VSS 22 VDD 7
A0
A1
A2
A3
A4
A5
A6
A7
A8
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
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A9
Specifications HIP7030A0
Absolute Maximum Ratings
DC Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V Input Voltage, VIN (Note 1) . . . . . . . . . . . . . (VSS-0.3) to (VDD+0.3)V Self-Check Mode (IRQ Pin Only), VIN . . (VSS-0.3) to 2*(VDD+0.3)V Current Drain Per Pin (Excluding VDD and VSS) . . . . . . . . . . 25mA
Thermal Information
Thermal Resistance JA Plastic LCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55oC/W Maximum Package Power Dissipation, PD at 125oC . . . . . . 450mW Operating Temperature Range . . . . . . . . . . . . . . . -40oC to +125oC Storage Temperature Range, TSTG . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Control Timing
VDD = 5VDC 10%, VSS = 0VDC , TA = -40oC to +125oC Unless Otherwise Specified. SYMBOL TEST CONDITION MIN TYP MAX UNITS
PARAMETER FREQUENCY OF OPERATION Crystal Option External Clock Option INTERNAL OPERATING FREQUENCY Crystal (fOSC + 2) External Clock (fOSC + 2) Cycle Time
fOSC
1 1
-
10 10
MHz MHz
fOP
0.5 0.5
-
5 5 -
MHz MHz ns
tCYC
200
DC Electrical Specifications
PARAMETER Output Voltage
VDD = 5VDC 10%, VSS = 0VDC , TA = -40oC to +125oC Unless Otherwise Specified. SYMBOL VOL VOH TEST CONDITION ILOAD < 10mA ILOAD > -10mA ILOAD = 0.8mA MIN VDD -0.1 VDD -0.8 TYP MAX 0.1 UNITS V V V
Output High Voltage: A0-A12, DB0-DB7, CE, RD, WE, FS Output Low Voltage: A0-A12, DB0-DB7, CE, RD, WE, FS Input High Voltage: DB0-DB7 Input Low Voltage: DB0-DB7 DB0-7 High Impedance Leakage Current: Input Current Capacitance
VOH
VOH
ILOAD = 1.6mA
-
-
0.4 0.7*VDD +10
V
VIH VIL IIL
0.3*VDD -10
0.5*VDD -
V V A A pF pF mA
IIN COUT CIN
-1 -
8
+1 12 8 TBD
Supply Current: RUN NOTES:
IRUN
1. This device contains circuitry to protect the inputs against damage due to high static voltages of electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that VIN and VOUT be constrained to the range VSS (VIN or VOUT) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either VSS or VDD) 2. Characteristics are listed for the signals unique to the Emulator IC. For details on the other signal pins see the HIP7030A2 data sheet. 3. Minimum frequency applies when ALC is low.
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Specifications HIP7030A0
Read Cycle Timing
NUMBER (ALC = 0) (See Figure 1) VDD = 5VDC 10%, VSS = 0VDC , TA = -40oC to +125oC Unless Otherwise Specified. PARAMETER OSCB Operating Frequency Read Cycle Time Address Setup Time Before CE Access Time From CE Access Time From RD Access Time From Address Change Address Hold Time After CE Data Hold Time After CE Data Bus Driven From RD (Time to Data Active from High Impedance State) Data Hold Time After RD (Hold Time to High Impedance State) OSCB to DS Propagation Delay MIN 1 200 -10 0 0 0 MAX 10 2000 tCYC - 80 0.75tCYC - 80 tCYC - 80 UNITS MHz ns ns ns ns ns ns ns ns
SYMBOL fOSC
(1) (2) (3) (4) (5) (6) (7) (8)
tCYC tAVCEL tDVCEL tDVRDL tDVAV tCEHAX tCEHAX tRDLDX
(9) (10) NOTE:
tRDHAX
0
-
ns
tOSCDS
5
25
ns
Minimum frequency applies when ALC is low.
Write Cycle Timing
NUMBER
(ALC = 0) (See Figure 2) VDD = 5VDC 10%, VSS = 0VDC , TA = -40oC to +125oC Unless Otherwise Specified. PARAMETER OSCB Operating Frequency Write Cycle Time Address Setup Time Before CE Address Setup Time Before WE WE Pulse Width Data Set-up Time to WE Trailing Edge Data Hold Time After WE Trailing Edge Address Hold Time After WE Trailing Edge OSCB to DS Propagation Delay MIN 1 200 -10 0.25tCYC - 25 0.5tCYC - 10 0.75tCYC - 75 0.25tCYC - 20 0.25tCYC - 20 5 MAX 10 2000 25 UNITS MHz ns ns ns ns ns ns ns
SYMBOL fOSC
(1) (2) (3) (4) (5) (6) (7) (8) NOTE:
tCYC tAVCEL tAVWEL tWEWE tDVWEH tWEHDX tWEHAX tOSCDS
1. Minimum frequency applies when ALC is low.
Read Cycle Timing (ALC = 1) (See Figure 3) VDD = 5VDC 10%, VSS = 0VDC, TA = -40oC to +125oC Unless Otherwise Specified.
NUMBER SYMBOL fOSC PARAMETER OSCB Operating Frequency MIN MAX 10 UNITS MHz
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Specifications HIP7030A0
Read Cycle Timing (ALC = 1) (See Figure 3) VDD = 5VDC 10%, VSS = 0VDC, TA = -40oC to +125oC Unless Otherwise Specified.
NUMBER (1) (2) (3) (4) (5) (6) (7) (8) SYMBOL tCYC tRDOSC tDVCEL tDVOSC tOSCAV tOSCAX tOSCAX tRDLDX PARAMETER Read Cycle Time RD, FS Setup Time Before OSCB Access Time From CE Access Time From OSCB Address Setup Time Before OSCB Address Hold Time After OSCB Data Hold Time After OSCB Data Bus Driven From CE (Time to Data Active from High Impedance State) RD, FS Hold Time After OSCB OSCB to DS Propagation Delay MIN 200 0.5tCYC-25 0.5tCYC-25 0.5tCYC 10 0 MAX tCYC-80 tCYC-70 UNITS ns ns ns ns ns ns ns ns
(9) (10) NOTE:
tOSCRD tOSCDS
0.5tCYC 5
25
ns ns
1. Minimum frequency applies when ALC is high.
Write Cycle Timing (ALC = 1) (See Figure 4) VDD = 5VDC 10%, VSS = 0VDC, TA = -40oC to +125oC Unless Otherwise Specified.
NUMBER SYMBOL fOSC (1) (2) (3) (4) (5) (6) (7) tCYC tRDOSC tDVOSC tOSCAV tOSCAX tOSCAX tOSCDX PARAMETER OSCB Operating Frequency Write Cycle Time RD, FS Setup Time Before OSCB Data Setup Time Before OSCB Address Setup Time Before OSCB Address Hold Time After OSCB Data Hold Time After OSCB Data Bus Driven From OSCB (Time to Data Active from High Impedance State) RD, FS Hold Time After OSCB OSCB to DS Propagation Delay 0.5tCYC-25 0.5tCYC 10 .25tCYC-25 200 0.5tCYC-25 MIN MAX 10 0.75tCYC-95 UNITS MHz ns ns ns ns ns ns ns
(8) (9) NOTE:
tOSCRD tOSCDS
0.5tCYC 5
25
ns ns
1. Minimum frequency applies when ALC is high.
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HIP7030A0
1 OSCB
DS
10
A0-A12
5
3 CE 2 6
RD
4
9
DB 8 7
NOTE: 1. Measurement points are VOL, VOH, VIL and VIH . FIGURE 1. READ CYCLE TIMING DIAGRAM (ALC = 0)
1 OSCB
DS
8
A0-A12
7
CE
2
WE
3
4
DB 5
6
NOTE: 1. Measurement points are VOL, VOH, VIL and VIH . FIGURE 2. WRITE CYCLE TIMING DIAGRAM (ALC = 0)
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HIP7030A0
1 7
OSCB 4 DS 10 5 A0-A12 6
3 CE
RD
2
9
DB 8
NOTES: 1. Measurement points are VOL, VOH, VIL and VIH . 2. Timing for FS is identical to RD timing. FIGURE 3. READ CYCLE TIMING DIAGRAM (ALC = 1)
1 OSCB
6
3 DS 9 4 A0-A12 5
CE
RD
2
8
DB 7
NOTES: 1. Measurement points are VOL, VOH, VIL and VIH . 2. Timing for FS is identical to RD timing. FIGURE 4. WRITE CYCLE TIMING DIAGRAM (ALC = 1)
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HIP7030A0
OSCB DS
A0-A12
CE RD
WE
FS DB
FETCH
READ (INTERNAL)
WRITE
FIGURE 5. SIGNAL TIMING DIAGRAM (ALC = 1)
Functional Pin Description
This section provides a brief description of each of the pins of the HIP7030A0 microcontroller. A more detailed discussion is contained in the HIP7030A2 data sheet. VDD and VSS (Power) Power is supplied to the MCU using these two pins. VDD is connected to the positive supply and VSS is connected to the negative supply. IRQ (Maskable Interrupt Request - Input) The IRQ pin is negative edge-sensitive triggering. A high to low transition on the input to the IRQ pin will produce an interrupt. In the event of an interrupt request, the MCU always completes the current instruction before it responds to the request. An internal mask can be used to inhibit the MCU from responding to IRQ interrupts. An edge-sensitive IRQ interrupt is generated if the IRQ pin is pulled low for at least one tILIH. The occurrence of the low going pulse is registered in a flip-flop and the IRQ interrupt will be recognized even if the IRQ pin has returned to a high state before the interrupt can be serviced. Once the edge-sensitive flip-flop is cleared (it is automatically cleared at the start of the interrupt service routine) the interrupt request is removed until the IRQ pin returns to a high level and once again goes low. RESET (Master Reset - Input) The HIP7030A2 contains an integrated Power-On Reset (POR) circuit and the RESET input is therefore not required for startup. It can be used to reset the MCU internal state and provides for an orderly re-start of the software after initial powerup. A low level on the RESET pin will reset the HIP7030A0. TCAP (Timer Capture - Input) The TCAP input controls the input capture feature for the onchip programmable timer system. The TCAP input is also used as the strobe signal to the Port D strobed outputs. TCMP (Timer Compare - Output) The TCMP pin provides an output for the output compare feature of the on-chip timer system. OSCIN (Oscillator Input - Input), OSCOUT (Oscillator Output - Output), OSCB (Oscillator Buffered Output - Output) OSCIN is the input and OSCOUT is the output of an inverter/ amplifier which can be used to build either a quartz crystal or ceramic resonator based clock oscillator. Alternatively the OSCIN input can be driven from any external clock source which satisfies the CMOS schmitt trigger input level requirements of the OSCIN pin. OSCB is a squared, buffered version of the OSCIN signal, available for driving one external CMOS load. See Electrical Specifications of the HIP7030A2 for output drive and input level specifications. The fundamental internal clock is derived by a divide-by-two of the external oscillator frequency (fOSC). All other internal clocks are also derived from the external frequency. These clocks include the input to the 16-bit Timer, the SPI Serial Clock (SCK), and the VPW Symbol Encoder/Decoder (SENDEC). PA0-PA7 (Port A - Input/Output) These eight I/O lines comprise Port A. The mode (i.e. - input or output) of each pin is software programmable. All Port A I/ O lines are configured as inputs during power-on or RESET.
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HIP7030A0
PD0-PD4 (Port D - Input/Output) These five I/O lines comprise Port D. As with PA0-PA7, the mode (i.e. - input or output) of each pin is software programmable. In addition a Special Function Register (SFRD) allows configuring PD0 and PD1 as "strobed" outputs, and/or PD2,PD3, and PD4 as inputs to an on-chip analog comparator. All Port D I/O lines are configured as inputs during power-on or RESET. VPWOUT (Variable Pulse Width Out - Output), VPWIN (Variable Pulse Width In - Input) These two lines are used to interface to the J1850 bus transceiver. VPWOUT is the pulse width modulated output of the SENDEC encoder block. VPWIN is the inverted input to the SENDEC decoder block. MISO (Master-in/Slave-out - Input/Output), MOSI (Master-out/Slave-in - Input/Output), SCK (Serial Clock - Input/Output), SS (Slave Select - Input) These four lines constitute the Serial Peripheral Interface (SPI) communications port. The MCU can be configured as a SPI "master" or as a SPI "slave". In master mode MOSI and SCK function as outputs and MISO functions as an input. In slave mode MOSI and SCK are inputs and MISO is an output. SS is always an input. Serial data words are transmitted and received over the MISO/MOSI lines synchronously with the SCK clock stream. The word size is fixed at 8 bits. Single buffering is used which results in an inherent inter-byte delay. The master device always provides the synchronizing clock. A low on the SS line causes the MCU to immediately assume the role of slave, regardless of it's current mode. This allows multi-master systems to be constructed with appropriate arbitration protocols. ALC (Address Latch Control - Input) The ALC input controls the timing and function of the address and memory control lines (CE, RD, WE, and FS). For more information on each of these lines refer to the appropriate section. When ALC is low the address and control lines are produced coincident with data bus transitions of the HIP7030A0's machine cycle. This mode allows direct interfacing to industry standard memory devices. Refer to the timing diagrams in Electrical Specifications for more details. Driving ALC high causes several changes in the behavior of the address and control lines. These changes are intended to facilitate design of development systems for the HIP7030A2. When ALC is high the following occur: * The Internal RAM is disabled and accesses to RAM space are mapped off-chip. * A0-A12, FS, and RD are produced tCYC cycle (i.e. 100ns with a 10MHz clock) ahead of data bus transitions of the HIP7030A0's machine cycle. The earlier availability of these address and control lines facilitates implementation of break detection and bus tracing logic. External latching of the address and control signals is required for interfacing to the memory of the development tool. The timing of CE and WE are not affected by ALC, and remain synchronized with data bus transfers. * The RD signal is no longer gated with CE and is a full cycle wide, when ALC is high. RD indicates whether the ensuing data bus cycle will be a read of or write to memory-I/O space. It can be viewed as a R/W signal. RD provides R/W information for all cycles, internal as well as external. * Resetting the HIP7030A0 with ALC = 1 disables the Slow Clock Detect circuits. The Watchdog can be disabled by writing to the Watchdog Status Register (WSR - location $1E), which has special features when ALC is high. The Slow Clock circuit is permanently disabled when ALC = 1. If the Slow Clock detect circuitry were allowed to run, stopping the CPU clock during breakpoint servicing would not be possible. The watchdog should be reset by the tool while interrogating the CPU. The ALC input has an integrated pull-down device which allows floating this pin when interfacing to industry standard memory devices. A0-A12 Address lines 0 through 12. When ALC = 0, A0-A12 are coincident with data bus transfers. When ALC = 1, A0-A12 change tCYC ahead of the data bus transfers and must be externally latched. See the timing diagrams in the Electrical Specifications section for more details. DB0-DB7 Bidirectional 8-bit non-multiplexed data bus lines. The data bus is an input during all reads from external memory-I/O space and during the first tCYC of every machine cycle. At all other times it is an output. See the timing diagrams in the Electrical Specifications section for more details. CE (Chip Enable - Output) Chip Enable is an output signal used for selecting external memory or I/O. A low level indicates when external memory or I/O is being accessed. Note that the CE signal will not go true when addressing the unused locations of Page 0 I/O space even though the address lines will be valid. RD (Read - Output) RD is a status output signal which indicates direction of data flow with respect to external or internal memory space (a low level indicates a read from memory space). A read from internal memory or I/O will place data on the external data
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HIP7030A0
bus. When ALC = 0, RD is internally gated with CE, and generated in synchronization with data bus cycles. With ALC = 0, standard RAM, ROM, and EPROM devices can be directly connected to the HIP7030A0 with no additional components. When ALC = 1, RD is not gated by CE and is produced tCYC cycle (i.e. 100ns with a 10MHz clock) ahead of data bus transitions of the HIP7030A0's machine cycle. WE (Write Enable - Output) Write Enable is an active low output pulse for use in writing data to external RAM memory. A low level indicates valid data on the data bus. WE is internally gated with CE for writing to external memory. Since, in most systems, external memory is substituting for mask programmed ROM, WE is frequently not used. DS (Data Strobe - Output) The Data Strobe output provides a pulse when address and data are valid. DS can be used to transfer data to or from a peripheral or memory and occurs every cycle and is also used for synchronizing development tools to the oscillator clock. DS is a continuous signal at fOSC / 2, except when the Emulator is in the WAIT or STOP mode. See the timing diagrams in the Electrical Specifications section for more details. FS (Fetch Status - Output) The FS output signal goes true to indicate an opcode fetch cycle is in progress. When ALC = 0, FS will be coincident with the data transfer of the fetch. When ALC = 1, FS is produced tCYC cycle (i.e. 100ns with a 10MHz clock) ahead of data bus transitions of the HIP7030A0's machine cycle. See the timing diagrams in the Electrical Specifications section for more details. may want to intentionally clear this bit to eliminate the need to insert watchdog handling routines. The clearing of the bit must be done following every reset. Reset presets the WDE bit of the WSR to enable the Watchdog Timer.
7 6 5 4 3 2 1 WDE 0 WDF
WATCHDOG STATUS REGISTER
Bit 7,6,5,4,3,2 - Unused Bit 1 - WDE When WDE (WatchDog Enable) is low, the Watchdog Timer is disabled. When ALC is high, WDE is forced high by any reset. The WDE bit should normally be cleared when servicing a breakpoint (if OSCIN is being clocked), to avoid a Watchdog Reset while interrogating the CPU. The WDE bit controls the Watchdog Reset, but it doesn't inhibit the Watchdog Timer from advancing. Prior to reenabling the WDE bit, the Watchdog Timer should normally be reset by writing $55, $AA to the Watchdog Reset Register (WDRR, location $1D). This implies that each breakpoint should generate a Watchdog Reset. To verify proper watchdog action the user should run final code with no breaks. In some cases the number of CPU cycles utilized in the break may be low enough to allow the watchdog to run without causing premature watchdog timeouts. Bit 0 - WDF The WatchDog flag (WDF), is set when a Watchdog timeout causes a COP Reset. This flag is used to distinguish a Slow Clock Detect from a Watchdog Timeout in the COP Reset service routine. Writing a 0 to the Watchdog Reset Register (WDRR, location $1D) clears the WDF flag. WDF is cleared by Power-on Reset, but unaffected by all other types of resets. For this reason, WDF should normally be cleared (by writing a 0 to the WDRR) following each read of the WSR.
Watchdog Status Register
When ALC is high, the HIP7030A0's Watchdog Status Register (WSR - location $1E) provides the ability to selectively enable and disable the Watchdog Timer logic of the HIP7030A0. The user of a development tool should be cautioned against accidently clearing the WDE bit of this register during final code prove-out. During initial code development the user
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